Integrated circuit designs can include multiple clock domain architectures/topologies, such as for multiple cores or functional blocks/modules. Clock distribution to the multiple clock domains can be based on a global input clock generator supplying a global clock (at a global clock frequency) to individual domain clock generators.
Within each clock domain, the domain clock generator generates a domain clock based on the global clock (and the global clock frequency), with the clock domain operating synchronously with the generated domain clock. Across clock domains, the generated domain clocks can be asynchronous in phase (cycle-to-cycle aperiodic). Dedicated interfaces manage inter-domain signaling, including synchronization.
That is, these multi-domain clock architectures are locally (inter-domain) synchronous but globally (intra-domain) asynchronous. This discrepancy in phase between clock domains can be referred to as clock/timing skew, which is a difference in edge timing between clock domains that affects cross-domain signaling or timing, which can be referred to as clock domain crossing operations.
An example of a multi-domain clock architecture is a direct conversion RF transmitter/transceiver. Direct conversion RF architectures commonly use quadrature (IQ) signal conversion and digital filtering. To meet requirements on out-of-band emissions, direct conversion transmitter designs commonly use digital pre-compensation for TX analog signal chain non-linearities and IQ mismatch (mismatch/imbalance between I and Q signal paths). In particular, IQ mismatch generate an images at frequencies reflected about the LO (local oscillator) frequency, which can appear in frequency bands outside the channel reserved for the TX (direct) signal.
IQ mismatch can be compensated by digital filtering referred to as QMC (IQ mismatch compensation). QMC is used to meet spectral emissions mask requirements for out-of-band interference, such as ACLR (adjacent channel leakage ratio) and ACPR (adjacent channel power ratio).
QMC compensation filtering in the TX signal path is based on QMC filter coefficients that require updating in a QMC calibration/adaptation operation (based on a QMC calibration/adaptation algorithm). A feedback receiver (FBRX) is used to capture data required for such calibration/adaptation. The TX and FBRX units are in different clock domains.
For TX QMC calibration/adaptation, a calibration signal is transmitted from the transmitter (TX) to the feedback receiver (FBRX), across the TX/FBRX clock domains. QMC calibration/adaptation relies on accurately estimating round-trip delay between TX calibration input and FBRX output. Specifically, convergence of the QMC calibration/adaptation algorithm relies on consistent round trip delay from capture interval to capture interval, so that the TX QMC calibration/adaptation algorithm's cost function can minimize the error between the TX input signal data set and the corresponding FBRX output signal data set (i.e., cost function minimization). The TX input data and resulting FBRX output data can be captured into respective TX and FBRX capture memories in the separate clock domains.
The asynchronous TX/FBRX domain clocks exhibit clock/timing (edge) skew that can affect the accuracy of the round-trip delay estimation required for QMC calibration (a clock domain crossing operation).
While this Background in in the context of direct conversion RF, with TX and FBRX clock domains, this Patent Disclosure is more generally related to clock generation in multi-domain clock architectures/topologies.